This invention relates to a semiconductor device which comprises an input buffer supplied with an input signal of an input level, such as a transistor/transistor logic (TTL) level, and a reference signal of a reference level to produce an output signal of an output level, such as a complementary metal-oxide semiconductor (CMOS) logic level, for use in the semiconductor device.
A complementary metal-oxide semiconductor device is suitable for large scale integration (LSI) and is therefore widely used in integrated semiconductor circuits (IC). Such complementary metal-oxide semiconductor devices are supplied with input signals which usually have the transistor/transistor logic level. On the other hand, the complementary metal-oxide semiconductor logic level is used in the complementary metal-oxide semiconductor devices. As a consequence, an input/output (I/O) interface is used in converting the transistor/transistor logic level to the complementary metal-oxide semiconductor logic level. The input buffer is used as the input/output interface and is designed to convert the transistor/transistor logic level to the complementary metal-oxide semiconductor logic level by comparing the transistor/transistor logic level with the reference level.
In the manner which will later be described in greater detail, a conventional semiconductor device of this type comprises on its semiconductor substrate an input buffer, an input signal pad supplied with an input signal of a source input level, such as the transistor/transistor logic level, an input signal connection for delivering the input signal to the input buffer, a reference signal pad supplied with a reference signal of a source reference level, and a reference signal connection for delivering the reference signal to the input buffer. Supplied with the input and the reference signals in this manner with a buffer input level and a buffer reference level, the input buffer compares the buffer input and reference levels with each other and produces an output signal with an output level, such as the complementary metal-oxide semiconductor logic level.
Each of the input and the reference signal connections has a parasitic resistance and a parasitic capacitance. The buffer input and reference levels are consequently different from the source input and reference levels. This gives rise to an objectionable delay in operation of the input buffer, particularly when noise is superimposed on the input and/or the reference signal connection.
In order to cope with the delay, an improved semiconductor device is disclosed in Japanese Patent Prepublication (A) No. 239,964 of 1989. This improved semiconductor device is excellently operable. The improved semiconductor device is, however, defective in that it unavoidably requires a wide chip area.
Another improved semiconductor device is revealed in Japanese Patent Prepublication (A) No. 120,743 of 1991. This improved semiconductor device is exqusitly operable but is disadvantageous as regards its inevitably wide chap area and noise superposed on the input and the reference signals by capacitive coupling between the substrate and the input and the reference signal connections through their parasitic capacitances.